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100K_0402_5%
USB_AS USB_BS
+3V
1 1
1 1
+ +
USB_CS
C33 C29 C20 C13
150U_D2_6.3VM 470P_0402_50V7K 150U_D2_6.3VM R5
2 2 2 2
R11 100K_0402_5%
+5V
2 470P_0402_50V7K 100K_0402_5% 2
U2
R185 JP6 R184 OVCUR#2
1 8
OVCUR#2 14
GND OC1#
0_0603_5% 0_0603_5%
1 5 2 7
VCC VCC IN OUT1
USB0- 2 6
USB5- 1 2
1 2 3 6
1
14 USBP0- D0- D1- USBP5- 14 EN1# OUT2
USB0+ USB5+
1 2 3 7 1 2 4 5
14 USBP0+ USBP5+ 14
D0+ D1+ EN2# OC2#
R186 R187 C14
4 8
VSS VSS
0_0603_5% 0_0603_5% 0.1U_0402_16V4Z TPS2042ADR_SO8
2
10 9
1 1 1 1
G2 G1
12 11
G4 G3
C23 C24
@470P_0603_50V8J SUYIN_2522A-08G2T-KU_8P @470P_0603_50V8J
2 2 2 2
USBEN#
C22
@470P_0603_50V8J C25
@470P_0603_50V8J
JP23
8
30 PWR_SUSP_LED
8
+3VALW
7
30,34 PWR_LED 7
+3VALW +3VALW
6
30 BATT_LOW_LED
6
5
30 BATT_CHGI_LED
5
4
30 WLLED
4
3 3
R422
3
30 BTLED
3
R420 R421
10K_0402_5% 2
2
10K_0402_5% 10K_0402_5% 1
1
ACES_85205-0800
3 1CAPS_LED#
28 CAPSLED#
PADS_LED# NUM_LED#
3 1 3 1
28 PADSLED# 28 NUMLED#
Q47
Q45 Q46 2SC2411K_SOT23
2SC2411K_SOT23 2SC2411K_SOT23
JP9
USER_BTN1# 28
1 2
3 4 USER_BTN2# 28
ON/OFFBTN# 30,34
5 6
PADS_LED#
7 8
NUM_LED#
+3VALW
9 10
CAPS_LED#
+5VS
Reserve For ABO 11 12
+5VALW
+5VALW 13 14 HDD_LED# 29
15 16 CD_FDD_LED# 29
SDLED
17 18 SDLED 24
19 20
R461
@100K_0402_5% SUYIN_80065A-020G2T
4 4
SDLED
D
Q52
2
28 SCROLLED#
G @2N7002_SOT23
S Compal Electronics, Inc.
Title
USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.3
DCL56 LA2231
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 05, 2004 Sheet 25 of 45
A B C D E
B
B
B
E
C
E
C
E
C
2
1
2
1
1
2
2
1
2
1
2
1
2
2
1
2
2
1
2
3
1
2
1
A B C D E
DTR#1
DTR#1 34
RTS#1
RTS#1 34
TXD1
SUPER I/O SMsC FDC47N217 TXD1 34
CTS#1
CTS#1 34
RI#1
RI#1 34
RXD1
RXD1 34
DCD#1
DCD#1 34
DSR#1
DSR#1 34
+3VS
RP37
DCD#1
1 1 8 1
RI#1
2 7
CTS#1
3 6
DSR#1
4 5
4.7K_8P4R_1206_5%
U32 R229
LPC_AD0 RXD1 1K_0402_5%
10 62 1 2
14,24,28 LPC_AD0 LAD0 RXD1
LPC_AD1 TXD1
12 63
14,24,28 LPC_AD1
LAD1 TXD1
LPC_AD2 DSR#1
13 64
14,24,28 LPC_AD2 LAD2 DSR1#
LPC_AD3 RTS#1
14 1
14,24,28 LPC_AD3 LAD3 RTS1#
CTS#1 +5V
2
CTS1#
LPC_FRAME# DTR#1
15 3
14,24,28 LPC_FRAME# LFRAME# DTR1#
LPC_DRQ#1 RI#1
16 4 JP27
14 LPC_DRQ#1 LDRQ# RI1#
DCD#1
5
DCD1#
17 1
7,13,19,20,21,22,23,24 PCIRST# PCI_RESET# 1
IRRX
1 2 18 37 2
IRRX 30
+3VS LPCPD# IRRX2 2
R248 10K_0402_5% RXD1
FIR 38 3
IRTXOUT 30
IRTX2 3
TXD1
19 39 4
IRMODE 30
14,19,23,28 PM_CLKRUN# CLKRUN# IRMODE/IRRX3 4
CLK_PCI_SIO DSR#1
20 5
12 CLK_PCI_SIO
PCI_CLK 5
LPTINIT# RTS#1
21 41 6
13,19,24,28 SIRQ LPTINIT# 27,34 6
SER_IRQ INIT#
LPTSLCTIN# CTS#1
1 2 6 42 7
+3VS IO_PME# SLCTIN# LPTSLCTIN# 27,34 7
R253 10K_0402_5% LPD0 DTR#1
44 8
LPD0 27,34
PD0 8
CLK_14M_SIO LPD1 RI#1
9 46 9
LPD1 27,34
12 CLK_14M_SIO CLK14 PD1 9
LPD2 DCD#1
CLOCK 47 10
LPD2 27,34
PD2 10
PID0 LPD3
23 48
17 PID0 LPD3 27,34
GPIO40 PD3
2 PID1 LPD4 @96212-1011S 2
24 49
17 PID1 GPIO41 PD4 LPD4 27,34
PID2 LPD5
25 50
17 PID2 LPD5 27,34
GPIO42 PD5
PID3 LPD6
27 51
17 PID3 LPD6 27,34
GPIO43 PD6
BT_DET LPD7
28 53
27 BT_DET LPD7 27,34
GPIO44 PD7
LPTSLCT
29 55
LPTSLCT 27,34
17 VGA_VID GPIO45 SLCT
LPTPE
1 2 30 56
+3VS GPIO46 PE LPTPE 27,34
R439 100K_0402_5% LPTBUSY
31 57
LPTBUSY 27,34
GPIO47 BUSY
LPTACK#
32 58
LPTACK# 27,34
GPIO10 ACK#
R226 1K_0402_5% LPTERR#
1 2 33 59
GPIO11/SYSOPT ERROR# LPTERR# 27,34
R223 10K_0402_5% LPTAFD#
1 2 34 60
+3VS GPIO12/IO_SMI# ALF# LPTAFD# 27,34
LPTSTB#
1 2 35 61
LPTSTB# 27,34
GPIO13/IRQIN1 STROBE#
R222 10K_0402_5% IRRX
36 1 2
GPIO14/IRQIN2
R219
1 2 40
GPIO23
R216 10K_0402_5% @1K_0402_5%
8 7
+3VS
VSS VTR
22 11
VSS VCC
43 POWER 26
VSS VCC
52 45
VSS VCC
54
VCC
C287
1 1 1 1
LPC47N217_STQFP64 C252 0.1U_0402_16V4Z
4.7U_0805_10V4Z
C316
2 2 2 2
C253
0.1U_0402_16V4Z 0.1U_0402_16V4Z
Base I/O Address
* 0 = 02Eh
1 = 04Eh
3 3
CLK_PCI_SIO CLK_14M_SIO
+3VS
RP36
R246 R252
10_0402_5% @10_0402_5% PID0
1 8
PID1
2 7
PID2
3 6
PID3
4 5
1 1
C302 C324 100K_8P4R_1206_5%
18P_0402_50V8K @10P_0402_25V8K
2 2
4 4
Compal Electronics, Inc.
Title
SUPER I/O
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
B 0.3
DCL56 LA2231
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 05, 2004 Sheet 26 of 45
A B C D E
I/
SERIAL
F
I/
LPC
F
I
GPIO
PARALLEL /F
2
1
2
1
JP10
1 2
31 MOD_MIC MDC_DN# 28
MONO_OUT/PC_BEEP AUDIO_PWDN
3 4
MD_SPK 31
GND MONO_PHONE
RFOFF# L7
5 6
AUXA_RIGHT Bluetooth Enable RFOFF# 28,30
CHB1608B121_0603
7 8
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