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Input leakage current ILI - -1.0 - 1.0 µA All input, All
input/output
Output leakage current ILO - -3.0 - 3.0 µA All
input/output,
All output
LCD driver ON resistance (1) V2RON V2=10.0V, Ta=25°C - 500 3000 &! COMn
LCD driver ON resistance (2) MV2 Vc=-7.0V, Ta=25°C - 500 3000 &! COMn
RON
LCD driver ON resistance (3) V1RON V1=2.5V,Io=|0.1|mA - 500 1800 &! SEGn,
Ta=25°C V1,MV1
LCD driver ON resistance (4) VCRON Vc=1.25V, Io=|0.1|mA - 400 2400 &! SEGn
Ta=25°C COMn
LCD power supply output impedance (1) VOUT 1/5 bias, C=1.0µF, - 200 400 &! VOUT
LCD power supply output impedance (2) V2 Ta=25°C - 2000 4000 &! V2
LCD power supply output impedance (3) MV2 - 1500 3000 &! MV2
LCD power supply output impedance (4) V1OUT Iout=±100µA, Ta=25°C - 100 200 &! V1OUT
Static current IDDQ Ta=25°C - 0.5 5 µA VDDI,
consumption VDD
I2Q V2=15.0V, Ta=25°C - 0.1 1 µA V2
I1Q V1=2.5V, Ta=25°C - 0.5 5 µA V1
Operating current consumption (1) IDD 1/6 bias, - 400 600 µA
IDDI fFR=85Hz, Vseg=3.3V, - 1 10 µA
normal mode
Operating current consumption (2) IDD MPU access under status (1). - 500 700 µA
IDDI tSCYC=1.5MHz - 10 20 µA
4096 colors, 15 fps equivalent
Operating current consumption (3) IDD 1/6 bias, - 300 500 µA
IDDI fFR=85Hz, Vseg=3.3V, - 1 10 µA
idle mode
Oscillation frequency fOSC1 Ta=25°C 714 840 966 kHz
fOSC2 Ta=25°C 33.0 39 43.5 kHz
Relationship between oscillation frequency fOSC1 and frame rate frequency fFR
fFR = fOSC1/(display duty)/(number of clock of per 1H)
Example: 840kHz/82/128 =80
Relationship between oscillation frequency fOSC2 and frame rate frequency fFR
fFR = fOSC2/(display duty)/(Dividing ratio×3)
Example: 39kHz/82/(2×3) = 80
Display duty and number of clocks of per 1H are set up by DISCTL command.
Rev.1.4 EPSON 63
S1D15G14 Series
11.2 I/O Circuit Diagram (For Reference)
1 I/O Pin (Both the input pin and the output pin are of the same structure.)
VDDI
Pin
GND
10k&! (Reference value)
2 Segment Driver
V1 V1
100&! (Reference value)
Pin
GND GND
3 Common Driver
V2
100&! (Reference value)
Pin
MV2 MV2
64 EPSON Rev.1.4
S1D15G14 Series
12. AC CHARACTERISTICS
12.1 9-bit Serial Interface
tCHW
___
CS
tCSH
tCSS
tr
tf
tSCYC
tSLW
tSHW
SCL
tSDS tSDH
SIO(Tx Data)
tACC tOH
SIO(Rx Data) Hi-Z
VDD = 2.6 to 3.6V, VDDI = 1.6 to VDD, Ta = -40 to +85°C
Parameter Signal Symbol Condition Min. Max. Unit
Serial clock cycle SCL tSCYC 75 - ns
Serial clock HIGH pulse width tSHW - 30 -
Serial clock LOW pulse width tSLW 30 -
Data setup time SIO tSDS 20 -
-
Data hold time tSDH 20 -
Data delay time (Hz-data) SIO tACC CL=30pF -
100
-
150
CL=100pF (reference)
Data delay time (data-Hz)
tOH CL=30pF 20
-
20
-
CL=100pF (reference)
___ ___
tCSS 40 -
CS serial clock time CS
tCSH - 40 -
tCSHW 40 -
Note1 The rise and fall times (tr and tf) of the input signal area specigied for less than 10ns.
Note2 Every timing is specified on the basis of 30% and 70% of VDDI.
VDD = 2.35 to 3.6V, VDDI = 1.6 to VDD, Ta = -40 to +85°C
Parameter Signal Symbol Condition Min. Max. Unit
Serial clock cycle SCL tSCYC 110 - ns
Serial clock HIGH pulse width tSHW - 50 -
Serial clock LOW pulse width tSLW 50 -
Data setup time SIO tSDS 25 -
-
Data hold time tSDH 25 -
Data delay time (Hz-data) SIO tACC CL=30pF -
120
-
180
CL=100pF (reference)
Data delay time (data-Hz)
tOH CL=30pF 25
-
25
-
CL=100pF (reference)
___ ___
tCSS 50 -
CS serial clock time CS
tCSH - 50 -
tCSHW 50 -
Note1 The input signal rise time and fall time (tr, tf) are specified less than 10 ns.
Note2 All timing signals are specified on the basis of 30% and 70% of VDDI.
Rev.1.4 EPSON 65
S1D15G14 Series
12.2 8-bit Serial Interface
tCHW
___
CS
tCSS tCSH
tf
tr
tSCYC
tSLW
tSHW
SCL
tSDS tSDH
SIO(Tx Data)
tACC tOH
Hi-Z
SIO(Rx Data)
tSAS
tSAH
A0
VDD = 2.6 to 3.6V, VDDI = 1.6 to VDD, Ta = -40 to +85°C
Parameter Signal Symbol Condition Min. Max. Unit
Serial clock cycle SCL tSCYC 75 - ns
Serial clock HIGH pulse width tSHW - 30 -
Serial clock LOW pulse width tSLW 30 -
Address setup time A0 tSAS 100 -
-
Address holds time tSAH 30 -
Data setup time SIO tSDS 20 -
-
Data hold time tSDH 20 -
Data delay time (Hz-data) SIO tACC CL=30pF - 100
CL=100pF (reference) - 150
Data delay time (data-Hz)
tOH CL=30pF 10 -
CL=100pF (reference) 20 -
___ ___
tCSS 50 -
CS serial clock time CS
tCSH - 50 -
tCSHW 50 -
Note1 The input signal rise time and fall time (tr, tf) are specified less than 10ns.
Note2 All timing signals are specified on the basis of 30% and 70% of VDDI.
66 EPSON Rev.1.4
S1D15G14 Series
VDD = 2.35 to 3.6V, VDDI = 1.6 to VDD, Ta = -40 to +85°C
Parameter Signal Symbol Condition Min. Max. Unit
Serial clock cycle SCL tSCYC 110 - ns
Serial clock HIGH pulse width tSHW - 50 -
Serial clock LOW pulse width tSLW 50 -
Address setup time A0 tSAS 120 -
-
Address hold time tSAH 30 -
Data setup time SIO tSDS 25 -
-
Data hold time tSDH 25 -
Data delay time (Hz-data) SIO tACC CL=30pF - 120
CL=100pF (reference) - 180
Data delay time (data-Hz)
tOH CL=30pF 15 -
CL=100pF (reference) 25 -
___ ___
tCSS 50 -
CS serial clock time CS
tCSH - 50 -
tCSHW 50 -
Note1 The input signal rise time and fall time (tr, tf) are specified less than 10ns.
Note2 All timing signals are specified on the basis of 30% and 70% of VDDI.
Rev.1.4 EPSON 67
S1D15G14 Series
12.3 68 Series Parallel Interface
A0,R/W
tAW6 tAH6
___
CS
tCW6
*1 tCCHW, tCCHR tCCLW , tCCLR
E
___
CS
tCYC , tCYC2
*2
E
tDS6 tDH6
D0 to D7
(write)
tACC6 tOH6
D0 to D7
(read)
______ ______
*1 shows an access with E when CS is LOW. *2 shows an access with CS when E is HIGH.
VDD = 2.6 to 3.6V, VDDI = 1.6 to VDD, Ta = -40 to +85°C
Parameter Signal Symbol Condition Min. Max. Unit
Address hold time A0,R/W tAH6 10 - ns
-
Address setup time tAW6 3 -
___
Write cycle E, CS tCYC 190 -
Read cycle tCYC2 250 -
Control pulse LOW width (write) tCCLW 140 -
Control pulse LOW width (read) tCCLR - 70 -
Control pulse HIGH width (write) tCCHW 40 -
Control pulse HIGH width (read) tCCHR 170 -
___
CS -E time tCW6 5 -
Data setup time D0 to D7 tDS6 10 -
-
Data hold time tDH6 20 -
Read access time tACC6 - 200
CL=100pF
Output disables time tOH6 5 60
Note1 The input signal rise time and fall time (tr, tf) are specified less than 10ns.
Note2 All timing signals are specified on the basis of 30% and 70% of VDDI.
68 EPSON Rev.1.4
S1D15G14 Series
VDD = 2.35 to 3.6V, VDDI = 1.6 to VDD, Ta = -40 to +85°C
Parameter Signal Symbol Condition Min. Max. Unit
Address hold time A0,R/W tAH6 15 - ns
-
Address setup time tAW6 5 -
___
Write cycle E, CS tCYC 250 -
Read cycle tCYC2 300 -
Control pulse LOW width (write) tCCLW 170 -
Control pulse LOW width (read) tCCLR - 80 -
Control pulse HIGH width (write) tCCHW 70 -
Control pulse HIGH width (read) tCCHR 200 -
___
CS -E time tCW6 10 -
Data setup time D0 to D7 tDS6 15 -
-
Data hold time tDH6 25 -
Read access time
tACC6 - 250
CL=100pF
Output disables time
tOH6 10 70
Note1 The input signal rise time and fall time (tr, tf) are specified less than 10ns.
Note2 All timing signals are specified on the basis of 30% and 70% of VDDI.
Rev.1.4 EPSON 69
S1D15G14 Series
12.4 80 Series Parallel Interface
A0
tAW8
___ tAH8
CS
tCW8
*1 tCCHW, tCCHR
___ ___
tCCLW , tCCLR
WR,RD
___
CS
tCYC , tCYC2
*2
___ ___
WR,RD
tDS8 tDH8
D0 to D7
(write)
tACC8 tOH8
D0 to D7
(read)
______ ______ ______ ______ ______
*1 shows an access with WR and RD when CS is LOW. *2 shows an access with CS when WR and
______
RD are LOW.
VDD = 2.6 to 3.6V, VDDI = 1.6 to VDD, Ta = -40 to +85°C
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